Digital Logic Design Quiz
Questions: 16 · 10 minutes
1. What primarily distinguishes an edge-triggered flip-flop from a level-sensitive latch?
A flip-flop can store multiple bits at once
A latch has no output until it is reset
A flip-flop samples its input around a clock edge
A latch always changes state on both clock edges
2. According to De Morgan’s theorem, which expression equals the complement of A AND B?
NOT A AND NOT B
NOT A OR B
A OR B
NOT A OR NOT B
3. A circuit is described by F = A + A′B. Which simplified expression is equivalent to F?
A + B
AB
A
B
4. A four-variable Karnaugh map contains 1s at minterms 0, 2, 8, and 10. What is the most efficient valid grouping?
Two separate groups of two with no edge wrapping
One group of four using wraparound adjacency
One diagonal group of four
Four individual groups of one
5. A positive-edge-triggered D flip-flop starts with Q = 0. The value of D at three successive rising clock edges is 1, then 0, then 1. What is Q immediately after the third edge?
0, because the initial state is retained
0, because the second edge cleared Q permanently
1, because Q captures the D value present at the third edge
Undefined, because D changed across multiple edges
6. Which gate outputs logic 1 when its two inputs have different logic values?
NOR
XNOR
XOR
AND
7. In a Mealy finite-state machine, what determines the output?
The current state and current input
Only the current input
Only the current state
The next state and previous output only
8. A 4-to-1 multiplexer has inputs D0 through D3. Under the usual binary selection convention, which input reaches the output when S1S0 = 10?
D0
D2
D1
D3
9. A warning lamp should turn on only when both sensor A and sensor B are at logic 1. Which single gate directly implements this behavior?
OR gate
XOR gate
NAND gate
AND gate
10. An active-low asynchronous reset on a flip-flop is asserted while the clock is not changing. What should happen to Q?
Q resets only at the next active clock edge
Q resets immediately without waiting for a clock edge
Q toggles once and then holds
Q follows the data input until reset is released
11. For F = AB + A′C, unequal gate delays can cause a static-1 hazard when A changes while B = C = 1. Which consensus term can be added to suppress this hazard?
BC
AC
B′C
A + B
12. A data input changes too close to the active clock edge and violates a flip-flop’s setup-time requirement. What is the main possible consequence?
The clock frequency automatically decreases
The captured value may be unpredictable, and metastability may occur
The flip-flop permanently behaves as a latch
The output is guaranteed to capture the new value
13. What is the minimum number of flip-flops required to represent all states of a modulo-10 counter?
3
10
5
4
14. A 3-to-8 active-high decoder receives the binary input 101. If exactly one output is asserted, which numbered output becomes logic 1?
Output 3
Output 4
Output 6
Output 5
15. What input distinguishes a full adder from a half adder?
An enable input
A clock input
A carry-in input
An active-low reset input
16. In Boolean algebra, what is the result of OR-ing variable A with logic 0?
The result remains A
The result is always logic 0
The result is always logic 1
The result becomes the complement of A